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| TC1302A/B Low Quiescent Current Dual Output LDO Features * Dual Output LDO: - VOUT1 = 1.5V to 3.3V @ 300 mA - VOUT2 = 1.5V to 3.3V @ 150 mA * Output Voltage (See Table 8-1) * Low Dropout Voltage: - VOUT1 = 104 mV @ 300 mA Typical - VOUT2 = 150 mV @ 150 mA Typical * Low Supply Current: 116 A Typical TC1302A/B with both output voltages available * Reference Bypass Input for Low-Noise Operation * Both Output Voltages Stable with a Minimum of 1 F Ceramic Output Capacitor * Separate VOUT1 and VOUT2 SHDN pins (TC1302B) * Power-Saving Shutdown Mode of Operation * Wake-up from SHDN: 5.3 s. Typical * Small 8-pin DFN or MSOP Package Options * Operating Junction Temperature Range: - -40C to +125C * Overtemperature and Overcurrent Protection Description The TC1302A/B combines two Low Dropout (LDO) regulators into a single 8-pin MSOP or DFN package. Both regulator outputs feature low dropout voltage, 104 mV @ 300 mA for VOUT1, 150 mV @ 150 mA for VOUT2, low quiescent current consumption, 58 A each and a typical regulation accuracy of 0.5%. Several fixed-output voltage combinations are available. A reference bypass pin is available to further reduce output noise and improve the power supply rejection ratio of both LDOs. The TC1302A/B is stable over all line and load conditions, with a minimum of 1 F of ceramic output capacitance, and utilizes a unique compensation scheme to provide fast dynamic response to sudden line voltage and load current changes. Additional features include an overcurrent limit and overtemperature protection that combine to provide a robust design for all load fault conditions. Package Types 8-Pin DFN/MSOP DFN8 NC 1 VOUT1 2 GND 3 Bypass 4 8 NC 7 VIN 6 VOUT2 Applications * * * * * * Cellular/GSM/PHS Phones Battery-Operated Systems Hand-Held Medical Instruments Portable Computers/PDAs Linear Post-Regulators for SMPS Pagers TC1302A NC 1 VOUT1 2 GND 3 MSOP8 8 NC 7 VIN 6 VOUT2 5 SHDN2 5 SHDN2 Bypass 4 Related Literature * AN765, "Using Microchip's Micropower LDOs", DS00765, Microchip Technology Inc., 2002 * AN766, "Pin-Compatible CMOS Upgrades to BiPolar LDOs", DS00766, Microchip Technology Inc., 2002 * AN792, "A Method to Determine How Much Power a SOT23 Can Dissipate in an Application", DS00792, Microchip Technology Inc., 2001 NC 1 VOUT1 2 GND 3 Bypass 4 DFN8 TC1302B NC 1 8 SHDN1 VOUT1 2 7 VIN 6 VOUT2 GND 3 5 SHDN2 Bypass 4 MSOP8 8 SHDN1 7 VIN 6 VOUT2 5 SHDN2 (c) 2005 Microchip Technology Inc. DS21333B-page 1 TC1302A/B Functional Block Diagrams TC1302A VIN LDO #1 300 mA VOUT1 VIN SHDN1 LDO #1 300 mA TC1302B VOUT1 VOUT2 SHDN2 LDO #2 150 mA SHDN2 LDO #2 150 mA VOUT2 GND Bypass Bandgap Reference 1.2V GND Bypass Bandgap Reference 1.2V Typical Application Circuits TC1302A 1 2.8V @ 300 mA COUT1 1 F Ceramic X5R CBYPASS 10 nF Ceramic (Note) NC NC 8 BATTERY CIN 1 F 2.7V to 4.2V 2V OUT1 3 4 GND VIN 7 VOUT2 6 2.6V @ 150 mA 5 COUT2 1 F Ceramic X5R Bypass SHDN2 ON/OFF Control VOUT2 ON/OFF Control VOUT1 TC1302B 1 2.8V @ 300 mA COUT1 1 F Ceramic X5R NC SHDN1 8 BATTERY CIN 1 F 2.7V to 4.2V 2V OUT1 3 4 GND VIN 7 VOUT2 6 2.6V @ 150 mA 5 Bypass SHDN2 COUT2 1 F Ceramic X5R Note: CBYPASS is optional ON/OFF Control VOUT2 DS21333B-page 2 (c) 2005 Microchip Technology Inc. TC1302A/B 1.0 ELECTRICAL CHARACTERISTICS Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings VDD...................................................................................6.5V Maximum Voltage on Any Pin ...... (VSS - 0.3) to (VIN + 0.3)V Power Dissipation ..........................Internally Limited (Note 7) Storage temperature .....................................-65C to +150C Maximum Junction Temperature, TJ ........................... +150C Continuous Operating Temperature Range ..-40C to +125C ESD protection on all pins, HBM, MM ..................... 4 kV, 400V DC CHARACTERISTICS Electrical Specifications: Unless otherwise noted, VIN = VR +1V, IOUT1 = IOUT2 = 100 A, CIN = 4.7 F, COUT1 = COUT2 = 1 F, CBYPASS = 10 nF, SHDN > VIH, TA = +25C. Boldface type specifications apply for junction temperatures of -40C to +125C. Parameters Input Operating Voltage Maximum Output Current Maximum Output Current Output Voltage Tolerance (VOUT1 and VOUT2) Temperature Coefficient (VOUT1 and VOUT2) Line Regulation (VOUT1 and VOUT2) Load Regulation, VOUT 2.5V (VOUT1 and VOUT2) Load Regulation, VOUT < 2.5V (VOUT1 and VOUT2) Thermal Regulation Dropout Voltage (Note 6) VOUT1 > 2.7V VOUT2 > 2.6V Supply Current TC1302A TC1302B Note 1: 2: 3: 4: IIN(A) IIN(B) -- -- 103 114 180 180 A A SHDN2 = VIN, IOUT1 = IOUT2 = 0 mA SHDN1 = SHDN2 = VIN, IOUT1 = IOUT2 = 0 mA VIN - VOUT VIN - VOUT -- -- 104 150 180 250 mV mV IOUT1 = 300 mA IOUT2 = 150 mA Sym VIN IOUT1Max IOUT2Max VOUT TCVOUT VOUT/VIN VOUT/ VOUT VOUT/ VOUT VOUT/PD Min 2.7 300 150 VR - 2.5 -- -- -1 -1.5 -- Typ -- -- -- Max 6.0 -- -- Units V mA mA % ppm/C %/V % % %/W Note 1 VIN = 2.7V to 6.0V (Note 1) VIN = 2.7V to 6.0V (Note 1) Note 2 Note 3 (VR + 1V) VIN 6V IOUTX = 0.1 mA to IOUTMax, (Note 4) IOUTX = 0.1 mA to IOUTMax, (Note 4) Note 5 Conditions VR0.5 VR + 2.5 25 0.02 0.1 0.1 0.04 -- 0.2 +1 +1.5 -- 5: 6: 7: The minimum VIN has to meet two conditions: VIN 2.7V and VIN VR + VDROPOUT. VR is defined as the higher of the two regulator nominal output voltages (VOUT1 or VOUT2). TCVOUT = ((VOUTmax - VOUTmin) * 106)/(VOUT * T). Regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 0.1 mA to the maximum specified output current. Changes in output voltage due to heating effects are covered by the thermal regulation specification. Thermal regulation is defined as the change in output voltage at a time t after a change in power dissipation is applied, excluding load or line regulation effects. Specifications are for a current pulse equal to ILMAX at VIN = 6V for t = 10 msec. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its value measured at a 1V differential. The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation causes the device to initiate thermal shutdown. (c) 2005 Microchip Technology Inc. DS21333B-page 3 TC1302A/B DC CHARACTERISTICS (Continued) Electrical Specifications: Unless otherwise noted, VIN = VR +1V, IOUT1 = IOUT2 = 100 A, CIN = 4.7 F, COUT1 = COUT2 = 1 F, CBYPASS = 10 nF, SHDN > VIH, TA = +25C. Boldface type specifications apply for junction temperatures of -40C to +125C. Parameters Shutdown Supply Current TC1302A Shutdown Supply Current TC1302B Power Supply Rejection Ratio Output Noise Output Short Circuit Current (Average) VOUT1 VOUT2 SHDN Input High Threshold SHDN Input Low Threshold Wake Up Time (From SHDN mode), (VOUT2) Settling Time (From SHDN mode), (VOUT2) Thermal Shutdown Die Temperature Thermal Shutdown Hysteresis Note 1: 2: 3: 4: IOUTsc1 IOUTsc2 VIH VIL tWK tS TSD THYS -- -- 45 -- -- -- -- -- 200 140 -- -- 5.3 50 150 10 -- -- -- 15 20 -- -- -- mA mA %VIN %VIN s s C C RLOAD1 1 RLOAD2 1 VIN = 2.7V to 6.0V VIN = 2.7V to 6.0V VIN = 5V, IOUT1 = IOUT2 = 30 mA, See Figure 5-1 VIN = 5V, IOUT1 = IOUT2 = 50 mA, See Figure 5-2 VIN = 5V, IOUT1 = IOUT2 = 100 A VIN = 5V Sym IIN_SHDNA IIN_SHDNB PSRR eN Min -- -- -- -- Typ 58 0.1 58 830 Max 90 1 -- -- Units A A dB Conditions SHDN2 = GND SHDN1 = SHDN2 = GND f 100 Hz, IOUT1 = IOUT2 = 50 mA, CIN = 0 F nV/(Hz)1/2 f 1 kHz, IOUT1 = IOUT2 = 50 mA, CIN = 0 F 5: 6: 7: The minimum VIN has to meet two conditions: VIN 2.7V and VIN VR + VDROPOUT. VR is defined as the higher of the two regulator nominal output voltages (VOUT1 or VOUT2). TCVOUT = ((VOUTmax - VOUTmin) * 106)/(VOUT * T). Regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 0.1 mA to the maximum specified output current. Changes in output voltage due to heating effects are covered by the thermal regulation specification. Thermal regulation is defined as the change in output voltage at a time t after a change in power dissipation is applied, excluding load or line regulation effects. Specifications are for a current pulse equal to ILMAX at VIN = 6V for t = 10 msec. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its value measured at a 1V differential. The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation causes the device to initiate thermal shutdown. TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all limits are specified for: VIN = +2.7V to +6.0V. Parameters Temperature Ranges Operating Junction Temperature Range Storage Temperature Range Maximum Junction Temperature Thermal Package Resistances Thermal Resistance, MSOP8 Thermal Resistance, DFN8 JA JA -- -- 208 41 -- -- C/W C/W Typical 4-Layer Board Typical 4-Layer Board with Vias TA TA TJ -40 -65 -- -- -- -- +125 +150 +150 C C C Transient Steady State Sym Min Typ Max Units Conditions DS21333B-page 4 (c) 2005 Microchip Technology Inc. TC1302A/B 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VIN = VR +1V, IOUT1 = IOUT2 = 100 A, CIN = 4.7 F, COUT1 = COUT2 = 1 F (X5R or X7R), CBYPASS = 0 pF, SHDN1 = SHDN2 > VIH, TA = +25C. 350 Quiescent Current (A) 300 250 200 150 100 50 0 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 6.0 Input Voltage (V) 2.60 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 Input Voltage (V) 6 VOUT2 Active VOUT2 SHDN TC1302B Output Voltage (V) TJ = +25C IOUT1 = IOUT2 = 0 A VOUT1 Active 3.00 2.90 VOUT1 TJ = +25C IOUT1 = 100 mA IOUT2 = 50 mA 2.80 2.70 VOUT2 FIGURE 2-1: Voltage. 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 2.7 3 Quiescent Current vs. Input FIGURE 2-4: Voltage. 2.90 2.85 Output Voltage (V) Output Voltage vs. Input SHDN Threshold (V) VOUT1 ON 2.80 2.75 2.70 2.65 2.60 2.55 2.50 VOUT2 TJ = +25C IOUT1 = 300 mA IOUT2 = 100 mA OFF 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 Input Voltage (V) 6 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 Input Voltage (V) 6 FIGURE 2-2: vs. Input Voltage. 140 130 120 110 100 90 80 70 60 50 40 SHDN Voltage Threshold FIGURE 2-5: Voltage. 140.0 120.0 100.0 80.0 60.0 40.0 20.0 0.0 0 50 Output Voltage vs. Input TC1302B VOUT2 Active Quiescent Current (A) VIN = 4.2V IOUT1 = IOUT2 = 0 A VOUT1 Active Dropout Voltage V OUT1 (mV) VR1 = 2.8V VR2 = 2.6V IOUT2 = 100 A TJ = +125C TJ = +25C VOUT2 SHDN TJ = - 40C -40 -25 -10 5 20 35 50 65 80 95 110 125 100 150 IOUT1 (mA) 200 250 300 Junction Temperature (C) FIGURE 2-3: Quiescent Current vs. Junction Temperature. FIGURE 2-6: Current (VOUT1). Dropout Voltage vs. Output (c) 2005 Microchip Technology Inc. DS21333B-page 5 TC1302A/B Note: Unless otherwise indicated, VIN = VR +1V, IOUT1 = IOUT2 = 100 A, CIN = 4.7 F, COUT1 = COUT2 = 1 F (X5R or X7R), CBYPASS = 0 pF, SHDN1 = SHDN2 > VIH, TA = +25C. 140 120 100 80 60 IOUT1 = 100 mA Dropout Voltage V OUT1 (mV) Load Regulation (%) VR1 = 2.8V VR2 = 2.6V IOUT2 = 100 A 0.40 IOUT1 = 300 mA 0.30 0.20 0.10 0.00 -0.10 -0.20 -0.30 -0.40 -40 -25 -10 5 VR1 = 2.8V VR2 = 2.6V VIN = 4.2 VOUT2 IOUT2 = 0.1 mA to 150 mA VOUT1 IOUT1 = 0.1 mA to 300 mA 40 20 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 IOUT1 = 50 mA 20 35 50 65 80 95 110 125 Junction Temperature (C) Junction Temperature (125C) FIGURE 2-7: Dropout Voltage vs. Junction Temperature (VOUT1). 180 160 140 120 100 80 60 40 20 0 0 Dropout Voltage, V OUT2 (mv) FIGURE 2-10: VOUT1 and VOUT2 Load Regulation vs. Junction Temperature. 0.045 Line Regulation (%/V) VR1 = 2.8V VR2 = 2.6V IOUT1 = 100 A TJ = +125C TJ = +25C TJ = - 40C 0.040 0.035 0.030 0.025 0.020 0.015 0.010 0.005 0.000 VOUT1 VOUT2 VIN = 3.8V to 6.0V VR1 = 2.8V, IOUT1 = 100 A VR2 = 2.6V, IOUT2 = 100 A 30 60 90 120 150 IOUT2 (mA) -40 -25 -10 5 20 35 50 65 80 95 110 125 Junction Temperature (C) FIGURE 2-8: Current (VOUT2). Dropout Voltage V OUT2 (mV) 180 160 140 120 100 80 60 40 20 0 -40 -25 -10 5 Dropout Voltage vs. Output FIGURE 2-11: VOUT1 and VOUT2 Line Regulation vs. Junction Temperature. 2.832 IOUT2 = 150 mA VR1 = 2.8V VR2 = 2.6V IOUT1 = 100 A Output Voltage V OUT1 (V) 2.828 2.824 2.820 2.816 2.812 2.808 VIN = 4.2V VR1 = 2.8V VR2 = 2.6V, IOUT2 = 100 A IOUT1 = 300 mA IOUT1 = 100 mA IOUT2 = 50 mA IOUT1 = 100 A IOUT2 = 10 mA 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Junction Temperature (C) Junction Temperature (C) FIGURE 2-9: Dropout Voltage vs. Junction Temperature (VOUT2). FIGURE 2-12: Temperature. VOUT1 vs. Junction DS21333B-page 6 (c) 2005 Microchip Technology Inc. TC1302A/B Note: Unless otherwise indicated, VIN = VR +1V, IOUT1 = IOUT2 = 100 A, CIN = 4.7 F, COUT1 = COUT2 = 1 F (X5R or X7R), CBYPASS = 0 pF, SHDN1 = SHDN2 > VIH, TA = +25C. 2.856 Output Voltage VOUT1 (V) 2.848 2.840 2.832 2.824 2.816 2.808 -40 -25 -10 5 20 35 50 65 80 95 110 125 VIN = 4.2V VIN = 6.0V VR1 = 2.8V, IOUT1 = 300 mA VR2 = 2.6V, IOUT2 = 100 A VIN = 3.0V Junction Temperature (C) FIGURE 2-13: Temperature. 2.645 Output Voltage VOUT2 (V) 2.640 2.635 2.630 2.625 2.620 2.615 -40 -25 -10 5 VOUT1 vs. Junction FIGURE 2-16: Power Supply Rejection Ratio vs. Frequency (without bypass capacitor). IOUT2 = 100 A IOUT2 = 50 mA IOUT2 = 150 mA VIN = 4.2V VR1 = 2.8V, IOUT1 = 100 A VR2 = 2.6V 20 35 50 65 80 95 110 125 Junction Temperature (C) FIGURE 2-14: Temperature. 2.644 Output Voltage V OUT2 (V) 2.640 2.636 2.632 2.628 2.624 -40 -25 -10 5 VOUT2 vs. Junction FIGURE 2-17: Power Supply Rejection Ratio vs. Frequency (with bypass capacitor). 10 VOUT2 VR1 = 2.8V, IOUT1 = 100 A VR2 = 2.6V, IOUT2 = 150 mA VIN = 4.2V VIN = 3.0V NOISE (V/ Hz) 1 VIN = 4.2V VR1 = 2.8V VR2=2.6V IOUT1 = 150 mA IOUT2 = 100 mA CBYPASS = 0 nF VOUT1 VIN = 6.0V 0.1 20 35 50 65 80 95 110 125 0.01 0.01 0.1 1 10 100 1000 Junction Temperature (C) Frequency (KHz) FIGURE 2-15: Temperature. VOUT2 vs. Junction FIGURE 2-18: VOUT1 and VOUT2 Noise vs. Frequency (without bypass capacitor). (c) 2005 Microchip Technology Inc. DS21333B-page 7 TC1302A/B Note: Unless otherwise indicated, VIN = VR +1V, IOUT1 = IOUT2 = 100 A, CIN = 4.7 F, COUT1 = COUT2 = 1 F (X5R or X7R), CBYPASS = 0 pF, SHDN1 = SHDN2 > VIH, TA = +25C. 10 NOISE (V/ Hz) 1 0.1 0.01 VIN = 4.2V VR1 = 2.8V VR2=2.6V IOUT1 = 150 mA IOUT2 = 100 mA CBYPASS = 10 nF VOUT1 VOUT2 0.001 0.01 0.1 1 10 100 1000 Frequency (KHz) FIGURE 2-19: VOUT1 and VOUT2 Noise vs. Frequency (with bypass capacitor). FIGURE 2-22: VOUT1 and VOUT2 Power-up from Input Voltage TC1302B. FIGURE 2-20: VOUT1 and VOUT2 Power-up from Shutdown TC1302B. FIGURE 2-23: Dynamic Line Response. FIGURE 2-21: VOUT2 Power-up from Shutdown Input TC1302A. FIGURE 2-24: VOUT1. 300 mA Dynamic Load Step DS21333B-page 8 (c) 2005 Microchip Technology Inc. TC1302A/B Note: Unless otherwise indicated, VIN = VR +1V, IOUT1 = IOUT2 = 100 A, CIN = 4.7 F, COUT1 = COUT2 = 1 F (X5R or X7R), CBYPASS = 0 pF, SHDN1 = SHDN2 > VIH, TA = +25C. FIGURE 2-25: VOUT2. 150 mA Dynamic Load Step (c) 2005 Microchip Technology Inc. DS21333B-page 9 TC1302A/B 3.0 TC1302A PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: Pin No. 1 2 3 4 5 6 7 8 TC1302A PIN FUNCTION TABLE Name NC VOUT1 GND Bypass SHDN2 VOUT2 VIN NC No connect. Regulated output voltage #1, capable of 300 mA. Circuit ground pin. Internal reference bypass pin. A 10 nF external capacitor can be used to further reduce output noise and improve PSRR performance. Output #2 shutdown control input. Regulated output voltage #2, capable of 150 mA. Unregulated input voltage pin. No connect. Function 3.1 Regulated Output Voltage #1 (VOUT1) 3.4 Output Voltage #2 Shutdown (SHDN2) Connect VOUT1 to the positive side of the VOUT1 capacitor and load. Capable of 300 mA maximum output current. VOUT1 output is available when VIN is available; there is no pin to turn it OFF. See TC1302B if ON/OFF control of VOUT1 is desired. ON/OFF control is performed by connecting SHDN2 to its proper level. When the input of this pin is connected to a voltage less than 15% of VIN, VOUT2 will be OFF. If this pin is connected to a voltage that is greater than 45% of VIN, VOUT2 will be turned ON. 3.2 Circuit Ground Pin (GND) 3.5 Connect GND to the negative side of the input and output capacitor. Only the LDO internal circuitry bias current flows out of this pin (200 A maximum). Regulated Output Voltage #2 (VOUT2) 3.3 Reference Bypass Input Connect VOUT2 to the positive side of the VOUT2 capacitor and load. This pin is capable of a maximum output current of 150 mA. VOUT2 can be turned ON and OFF using SHDN2. By connecting an external 10 nF capacitor (typical) to the Bypass Input, both outputs (VOUT1 and VOUT2) will have less noise and improved Power Supply Ripple Rejection (PSRR) performance. The LDO output voltage start-up time will increase with the addition of an external bypass capacitor. By leaving this pin unconnected, the start-up time will be minimized. 3.6 Unregulated Input Voltage Pin (VIN) Connect the unregulated input voltage source to VIN. If the input voltage source is located more than several inches away or is a battery, a typical input capacitance of 1 F to 4.7 F is recommended. DS21333B-page 10 (c) 2005 Microchip Technology Inc. TC1302A/B 4.0 TC1302B PIN DESCRIPTIONS The descriptions of the pins are listed in Table 4-1. TABLE 4-1: Pin No. 1 2 3 4 5 6 7 8 TC1302B PIN FUNCTION TABLE Name NC VOUT1 GND Bypass SHDN2 VOUT2 VIN SHDN1 No connect. Regulated output voltage #1, capable of 300 mA. Circuit ground pin. Internal reference bypass pin. A 10 nF external capacitor can be used to further reduce output noise and improve PSRR performance. Output #2 shutdown control input. Regulated output voltage #2, capable of 150 mA. Unregulated Input voltage pin. Output #1 shutdown control input. Function 4.1 Regulated Output Voltage #1 (VOUT1) 4.5 Regulated Output Voltage #2 (VOUT2) Connect VOUT1 to the positive side of the VOUT1 capacitor and load. Capable of 300 mA maximum output current. For the TC1302B, VOUT1 can be turned ON and OFF using the SHDN1 input pin. Connect VOUT2 to the positive side of the VOUT2 capacitor and load. This pin is capable of a maximum output current of 150 mA. VOUT2 can be turned ON and OFF using SHDN2. 4.2 Circuit Ground Pin (GND) 4.6 Connect GND to the negative side of the input and output capacitor. Only the LDO internal circuitry bias current flows out of this pin (200 A maximum). Unregulated Input Voltage Pin (VIN) 4.3 Reference Bypass Input Connect the unregulated input voltage source to VIN. If the input voltage source is located more than several inches away, or is a battery, a typical minimum input capacitance of 1 F and 4.7 F is recommended. By connecting an external 10 nF capacitor (typical) to the bypass input, both outputs (VOUT1 and VOUT2) will have less noise and improved Power Supply Ripple Rejection (PSRR) performance. The LDO output voltage startup time will increase with the addition of an external bypass capacitor. By leaving this pin unconnected, the startup time will be minimized. 4.7 Output Voltage #1 Shutdown (SHDN1) 4.4 Output Voltage #2 Shutdown (SHDN2) ON/OFF control is performed by connecting SNDN1 to its proper level. When this pin is connected to a voltage less than 15% of VIN, VOUT1 will be OFF. If this pin is connected to a voltage that is greater than 45% of VIN, VOUT1 will be turned ON. ON/OFF control is performed by connecting SHDN2 to its proper level. When this pin is connected to a voltage less than 15% of VIN, VOUT2 will be OFF. If this pin is connected to a voltage that is greater than 45% of VIN, VOUT2 will be turned ON. (c) 2005 Microchip Technology Inc. DS21333B-page 11 TC1302A/B 5.0 5.1 DETAILED DESCRIPTION Device Overview 5.5 Output Capacitor The TC1302A/B is a combination device consisting of one 300 mA LDO regulator with a fixed output voltage VOUT1 (1.5V - 3.3V) and one 150 mA LDO regulator with a fixed output voltage VOUT2 (1.5V - 3.3V). For the TC1302A, the 300 mA output (VOUT1) is always present, independent of the level of SHDN2. The 150 mA output (VOUT2) can be turned ON/OFF by controlling the level of SHDN2. For the TC1302B, VOUT1 and VOUT2 each have independent shutdown input pins (SHDN1 and SHDN2) to control their respective outputs. 5.2 LDO Output #1 LDO output #1 is rated for 300 mA of output current. The typical dropout voltage for VOUT1 = 104 mV @ 300 mA. A 1 F (minimum) output capacitor is needed for stability and should be located as close to the VOUT1 pin and ground as possible. A minimum output capacitance of 1 F for each of the TC1302A/B LDO outputs is necessary for stability. Ceramic capacitors are recommended because of their size, cost and environmental robustness qualities. Tantalum or aluminum electrolytic capacitors can be used on the LDO outputs as well. The Equivalent Series Resistance (ESR) requirements on the electrolytic output capacitor's are between 0 and 2 ohms. The output capacitor should be located as close to the LDO output as is practical. Ceramic materials, X7R and X5R, have low temperature coefficients and are well within the acceptable ESR range required. A typical 1 uF X5R 0805 capacitor has an ESR of 50 milliohms. Larger LDO output capacitors can be used with the TC1302A/B to improve dynamic performance and power supply ripple rejection performance. A maximum of 10 F is recommended. Aluminum electrolytic capacitors are not recommended for low temperature applications of < -25 C. 5.6 Bypass Input 5.3 LDO Output #2 LDO output #2 is rated for 150 mA of output current. The typical dropout voltage for VOUT2 = 150 mV. A 1 F (minimum) capacitor is needed for stability and should be located as close to the VOUT2 pin and ground as possible. 5.4 Input Capacitor The Bypass pin is connected to the internal LDO reference. By adding capacitance to this pin, the LDO ripple rejection, input voltage transient response and output noise performance are all increased. A typical bypass capacitor between 470 pF to 10 nF is recommended. Larger bypass capacitors can be used, but result in a longer time period for the LDO outputs to reach their rated output voltage when started from SHDN or VIN. Low input source impedance is necessary for the two LDO outputs to operate properly. When operating from batteries, or in applications with long lead length (> 10 inches) between the input source and the LDO, some input capacitance is recommended. A minimum of 1.0 F to 4.7 F is recommended for most applications. When using large capacitors on the LDO outputs, larger capacitance is recommended on the LDO input. The capacitor should be placed as close to the input of the LDO as is practical. Larger input capacitors will help reduce the input impedance and further reduce any high-frequency noise on the input and output of the LDO. 5.7 GND For the optimal noise and PSRR performance, the GND pin of the TC1302A/B should be tied to a quiet circuit ground. For applications that have switching or noisy inputs, tie the GND pin to the return of the output capacitor. Ground planes help lower inductance and voltage spikes caused by fast transient load currents and are recommended for applications that are subjected to fast load transients. 5.8 SHDN1/SHDN2 Operation The TC1302A SHDN2 pin is used to turn VOUT2 ON and OFF. A logic-high level on SHDN2 will enable the VOUT2 output, while a logic-low on the SHDN2 pin will disable the VOUT2 output. For the TC1302A, VOUT1 is not affected by SHDN2 and will be enabled as long as the input voltage is present. The TC1302B SHDN1 and SHDN2 pins are used to turn VOUT1 and VOUT2 ON and OFF. They operate independent of each other. DS21333B-page 12 (c) 2005 Microchip Technology Inc. TC1302A/B 5.9 TC1302A SHDN2 Timing 5.11 5.11.1 Device Protection OVERCURRENT LIMIT VOUT1 will rise independent of the level of SHDN2 for the TC1302A. Figure 5-1 is used to define the wake-up time from shutdown (tWK) and the settling time (tS). The wake-up time is dependant upon the frequency of operation. The faster the SHDN pin is pulsed, the shorter the wake-up time will be. In the event of a faulted output load, the maximum current the LDO output will permit to flow is limited internally for each of the TC1302A/B outputs. The peak current limit for VOUT1 is typically 1.1A, while the peak current limit for VOUT2 is typically 0.5A. During shortcircuit operation, the average current is limited to 200 mA for VOUT1 and 140 mA for VOUT2. VIN ts twk SHDN2 5.11.2 OVERTEMPERATURE PROTECTION VOUT1 If the internal power dissipation within the TC1302A/B is excessive due to a faulted load or higher-thanspecified line voltage, an internal temperature-sensing element will prevent the junction temperature from exceeding approximately 150C. If the junction temperature does reach 150C, both outputs will be disabled until the junction temperature cools to approximately 140C and the device resumes normal operation. If the internal power dissipation continues to be excessive, the device will again shut off. VOUT2 FIGURE 5-1: TC1302A Timing. 5.10 TC1302B SHDN1/SHDN2 Timing For the TC1302B, the SHDN1 input pin is used to control VOUT1. The SHDN2 input pin is used to control VOUT2, independent of the logic input on SHDN1. VIN ts twk SHDN1 VOUT1 SHDN2 VOUT2 FIGURE 5-2: TC1302B Timing. (c) 2005 Microchip Technology Inc. DS21333B-page 13 TC1302A/B 6.0 6.1 APPLICATION CIRCUITS/ ISSUES Typical Application EQUATION 6-1: P LDO = ( V IN ( MAX ) ) - V OUT ( MIN ) ) x I OUT ( MAX ) ) PLDO = LDO Pass device internal power dissipation VIN(MAX) = Maximum input voltage VOUT(MIN)= LDO minimum output voltage The TC1302A/B is used for applications that require the integration of two LDOs. TC1302A 1 2.8V @ 300 mA COUT1 1 F Ceramic X5R Cbypass 10 nF Ceramic 2 3 4 NC VOUT1 GND NC 8 BATTERY CIN 1 F 2.7V to 4.2V 1.8V 6 @ 150 mA VIN 7 VOUT2 Bypass SHDN2 5 COUT2 1 F Ceramic X5R In addition to the LDO pass element power dissipation, there is power dissipation within the TC1302A/B as a result of quiescent or ground current. The power dissipation, as a result of the ground current, can be calculated using the following equation. EQUATION 6-2: P I ( GND ) = VIN ( MAX ) x I VIN PI(GND) = Total current in ground pin. VIN(MAX) = Maximum input voltage. IVIN = Current flowing in the VIN pin with no output current on either LDO output. 2.7V to 4.2V ON/OFF Control VOUT2 ON/OFF Control VOUT1 TC1302B 1 2.8V @ 300 mA 2 COUT1 1 F Ceramic X5R 3 4 NC VOUT1 GND SHDN1 8 BATTERY CIN 1 F VIN 7 1.8V VOUT2 6 @ 150 mA 5 Bypass SHDN2 COUT2 1 F Ceramic X5R ON/OFF Control VOUT2 FIGURE 6-1: TC1302A/B. 6.1.1 Typical Application Circuit The total power dissipated within the TC1302A/B is the sum of the power dissipated in both of the LDOs and the P(IGND) term. Because of the CMOS construction, the typical IGND for the TC1302A/B is 116 A. Operating at a maximum of 4.2V results in a power dissipation of 0.5 milliWatts. For most applications, this is small compared to the LDO pass device power dissipation and can be neglected. The maximum continuous operating junction temperature specified for the TC1302A/B is +125C. To estimate the internal junction temperature of the TC1302A/B, the total internal power dissipation is multiplied by the thermal resistance from junction to ambient (RJA) of the device. The thermal resistance from junction-to-ambient for the 3x3DFN8 pin package is estimated at 41 C/W. APPLICATION INPUT CONDITIONS Package Type = 3x3DFN8 Input Voltage Range = 2.7V to 4.2V VIN maximum = 4.2V VIN typical = 3.6V VOUT1 = 300 mA maximum VOUT2 = 150 mA maximum EQUATION 6-3: 6.2 6.2.1 Power Calculations POWER DISSIPATION T J ( MAX ) = P TOTAL x R JA + T AMAX TJ(MAX) = Maximum continuous junction temperature. PTOTAL = Total device power dissipation. = Thermal resistance from junction RJA to ambient. TAMAX = Maximum Ambient Temperature. The internal power dissipation within the TC1302A/B is a function of input voltage, output voltage, output current and quiescent current. The following equation can be used to calculate the internal power dissipation for each LDO. DS21333B-page 14 (c) 2005 Microchip Technology Inc. TC1302A/B The maximum power dissipation capability for a package can be calculated given the junction-toambient thermal resistance and the maximum ambient temperature for the application. The following equation can be used to determine the package maximum internal power dissipation. Maximum Ambient Temperature TA(MAX) = 50C Internal Power Dissipation Internal power dissipation is the sum of the power dissipation for each LDO pass device. PLDO1(MAX) = (VIN(MAX) - VOUT1(MIN)) x IOUT1(MAX) PLDO1 = (4.2V - (0.975 x 2.8V)) x 300 mA PLDO1 = 441.0 milliWatts PLDO2 = (4.2V - (0.975 X 1.8V)) x 150 mA PLDO2 = 366.8 milliWatts PTOTAL = PLDO1 + PLDO2 PTOTAL= 807.8 milliWatts EQUATION 6-4: ( T J ( MAX ) - T A ( MAX ) ) P D ( MAX ) = --------------------------------------------------R JA PD(MAX) = maximum device power dissipation. TJ(MAX) = maximum continuous junction temperature. TA(MAX) = maximum ambient temperature. = Thermal resistance from junction to RJA ambient. Device Junction Temperature Rise EQUATION 6-5: T J ( RISE ) = P D ( MAX ) x R JA TJ(RISE) = Rise in device junction temperature over the ambient temperature. PD(MAX) = Maximum device power dissipation. = Thermal resistance from junction-toRJA ambient. The internal junction temperature rise is a function of internal power dissipation and the thermal resistance from junction to ambient for the application. The thermal resistance from junction to ambient (RJA) is derived from an EIA/JEDEC standard for measuring thermal resistance for small surface-mount packages. The EIA/JEDEC specification is JESD51-7 "High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages". The standard describes the test method and board specifications for measuring the thermal resistance from junction to ambient. The actual thermal resistance for a particular application can vary depending on many factors, such as copper area and thickness. Refer to AN792, "A Method to Determine How Much Power a SOT23 Can Dissipate in an Application", (DS00792), for more information regarding this subject. TJ(RISE) = PTOTAL x RqJA TJRISE = 807.8 milliWatts x 41.0 C/W TJRISE = 33.1C EQUATION 6-6: T J = T J ( RISE ) + T A = Junction temperature. TJ TJ(RISE) = Rise in device junction temperature over the ambient temperature. = Ambient Temperature. TA 6.3 Typical Application Internal power dissipation, junction temperature rise, junction temperature and maximum power dissipation are calculated in the following example. The power dissipation, as a result of ground current, is small enough to be neglected. Junction Temperature Estimate To estimate the internal junction temperature, the calculated temperature rise is added to the ambient or offset temperature. For this example, the worst-case junction temperature is estimated below. TJ = TJRISE + TA(MAX) TJ = 83.1C Maximum Package Power Dissipation at 50C Ambient Temperature 3x3DFN8 (41C/Watt RJA) PD(MAX) = (125C - 50C)/41 C/W PD(MAX) = 1.83 Watts MSOP8 (208C/Watt RJA) PD(MAX) = (125C - 50C)/208 C/W PD(MAX) = 0.360 Watts 6.3.1 Package POWER DISSIPATION EXAMPLE Package Type = 3x3DFN8 Input Voltage VIN = 2.7V to 4.2V LDO Output Voltages and Currents VOUT1 = 2.8V IOUT1 = 300 mA VOUT2 = 1.8V IOUT2 = 150 mA (c) 2005 Microchip Technology Inc. DS21333B-page 15 TC1302A/B 7.0 TYPICAL LAYOUT 8.0 8.1 ADDITIONAL OUTPUT VOLTAGES Output Voltage Options Table 8-1 describes the range of output voltage options available for the TC1302A/B. VOUT1 and VOUT2 can be factory preset from 1.5V to 3.3V in 100 mV increments. TABLE 8-1: VOUT1 CUSTOM OUTPUT VOLTAGES VOUT2 1.5V to 3.3V 1.5V to 3.3V For a listing of TC1302A/B standard parts, refer to the Product Identification System on page 23. FIGURE 7-1: MSOP8 Silk-screen Layer. When designing the physical layout for the TC1302A/B, the highest priority should be placed on positioning the input and output capacitors as close to the device pins as is practical. Figure 7-1 above represents a typical placement of the components when using the SMT0805 capacitors. FIGURE 7-2: Example. DFN3x3 Silk-screen Figure 7-2 above represents a typical placement of the components when using the SMT0603 capacitors. DS21333B-page 16 (c) 2005 Microchip Technology Inc. TC1302A/B 9.0 9.1 PACKAGING INFORMATION Package Marking Information 8-Lead MSOP Example: -- 32A = TC1302A -- F = 2.8V VOUT1 -- H = 2.6V VOUT2 8-Lead DFN XXXX YYWW NNN Example: BFH 0542 256 XXXXXX YWWNNN 32AFH 542256 X1 represents VOUT1 configuration: Code A B C D E F G H I VOUT1 3.3V 3.2V 3.1V 3.0V 2.9V 2.8V 2.7V 2.6V 2.5V Code J K L M N O P Q R VOUT1 2.4V 2.3V 2.2V 2.1V 2.0V 1.9V 1.8V 1.7V 1.6V Code S T U V W X Y Z VOUT1 1.5V 1.65V 2.85V 2.65V 1.85V -- -- -- X2 represents VOUT2 configuration: Code A B C D E F G H I VOUT2 3.3V 3.2V 3.1V 3.0V 2.9V 2.8V 2.7V 2.6V 2.5V Code J K L M N O P Q R VOUT1 2.4V 2.3V 2.2V 2.1V 2.0V 1.9V 1.8V 1.7V 1.6V Code S T U V W X Y Z VOUT2 1.5V 1.65V 2.85V 2.65V 1.85V -- -- -- For a listing of TC1302A/B standard parts, refer to the Product Identification System on page 23. Legend: XX...X Y YY WW NNN e3 * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2005 Microchip Technology Inc. DS21333B-page 17 TC1302A/B 8-Lead Plastic Micro Small Outline Package (UA) (MSOP) E E1 p D 2 B n 1 A c A1 (F) A2 L 8 Number of Pins .026 BSC Pitch A .043 Overall Height A2 .030 .033 .037 Molded Package Thickness A1 .000 .006 Standoff E .193 TYP. Overall Width E1 .118 BSC Molded Package Width D .118 BSC Overall Length L .016 .024 .031 Foot Length Footprint (Reference) F .037 REF Foot Angle 0 8 c Lead Thickness .003 .006 .009 B .009 .012 .016 Lead Width 5 15 Mold Draft Angle Top 5 15 Mold Draft Angle Bottom *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. Units Dimension Limits n p MIN INCHES NOM MAX MIN MILLIMETERS* NOM 8 0.65 BSC 0.75 0.85 0.00 4.90 BSC 3.00 BSC 3.00 BSC 0.40 0.60 0.95 REF 0 0.08 0.22 5 5 - MAX 1.10 0.95 0.15 0.80 8 0.23 0.40 15 15 JEDEC Equivalent: MO-187 Drawing No. C04-111 DS21333B-page 18 (c) 2005 Microchip Technology Inc. TC1302A/B 8-Lead Plastic Dual Flat No Lead Package (MF) 3x3x0.9 mm Body (DFN) E p b n L D D2 EXPOSED METAL PAD E2 2 1 PIN 1 ID INDEX AREA (NOTE 2) TOP VIEW BOTTOM VIEW A3 A1 A EXPOSED TIE BAR (NOTE 1) Number of Pins Pitch Overall Height Standoff Lead Thickness Overall Length Exposed Pad Length Overall Width Exposed Pad Width Lead Width Lead Length Units Dimension Limits n p A A1 A3 E E2 D D2 b L MIN INCHES NOM 8 .026 BSC .035 .001 .008 REF. .118 BSC .118 BSC MAX MIN .031 .000 .039 .002 (Note 4) .055 .047 .007 .012 .096 .069 .015 .022 (Note 4) .010 .019 MILLIMETERS* NOM 8 0.65 BSC 0.80 0.90 0.02 0.00 0.20 REF. 3.00 BSC 1.39 3.00 BSC 1.20 0.26 0.23 0.30 0.48 MAX 1.00 0.05 2.45 1.75 0.37 0.55 *Controlling Parameter Notes: 1. Package may have one or more exposed tie bars at ends. 2. Pin 1 visual index feature may vary, but must be located within the hatched area. 3. Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. 4. Exposed pad dimensions vary with paddle size. 5. JEDEC equivalent: Pending Drawing No. C04-062 (c) 2005 Microchip Technology Inc. DS21333B-page 19 TC1302A/B NOTES: DS21333B-page 20 (c) 2005 Microchip Technology Inc. TC1302A/B APPENDIX A: REVISION HISTORY Revision B (January 2005) The following is the list of modifications: 1. Correct the incorrect part number options shown on the Product Identification System page and change the "standard" output voltage and reset voltage combinations. Added Appendix A: Revision History. 2. Revision A (September 2003) Original data sheet release. (c) 2005 Microchip Technology Inc. DS21333B-page 21 TC1302A/B NOTES: DS21333B-page 22 (c) 2005 Microchip Technology Inc. TC1302A/B PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. TC1302 XType A/B X VOUT1 X VOUT2 X XX XX Examples: a) TC1302ADTVMF: 3.0, 1.65, 8LD DFN pkg. 3.0, 1.65, 8LD DFN pkg. 2.6, 1.8, 8LD DFN pkg, Tape and Reel. 2.5, 1.8, 8LD MSOP pkg. Standard Configurations Device: Temp Package Tube or Range Tape & Reel a) b) TC1302BDTVMF: TC1302BHPVMFTR: TC1302A: Dual Output LDO with Single Shutdown input. TC1302B: Dual Output LDO with Dual Shutdown Inputs. c) TC1302BIPVUA: Standard Configurations: * TC1302A TC1302B VOUT1/VOUT2 3.0/1.65 3.0/1.65 2.6/1.8 2.5/1.8 Configuration Code DT DT HP IP * Contact Factory for Alternate Output Voltage Configurations. Temperature Range: V = -40C to +125C Package: MF UA = Dual Flat, No Lead (3x3 mm body), 8-lead = Plastic Micro Small Outline (MSOP), 8-lead Tube or Tape and Reel: Blank TR = Tube = Tape and Reel (c) 2005 Microchip Technology Inc. DS21333B-page 23 TC1302A/B NOTES: DS21333B-page 24 (c) 2005 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2005 Microchip Technology Inc. DS21333B-page 25 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Alpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307 Boston Westford, MA Tel: 978-692-3848 Fax: 978-692-3821 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 San Jose Mountain View, CA Tel: 650-215-1444 Fax: 650-961-0286 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8676-6200 Fax: 86-28-8676-6599 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Qingdao Tel: 86-532-502-7355 Fax: 86-532-502-7205 ASIA/PACIFIC India - Bangalore Tel: 91-80-2229-0061 Fax: 91-80-2229-0062 India - New Delhi Tel: 91-11-5160-8631 Fax: 91-11-5160-8632 Japan - Kanagawa Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Taiwan - Hsinchu Tel: 886-3-572-9526 Fax: 886-3-572-6459 EUROPE Austria - Weis Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Ballerup Tel: 45-4450-2828 Fax: 45-4485-2829 France - Massy Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Ismaning Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 England - Berkshire Tel: 44-118-921-5869 Fax: 44-118-921-5820 10/20/04 DS21333B-page 26 (c) 2005 Microchip Technology Inc. |
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